A gate-coupling coefficient may be an important element in determining an efficiency of a memory cell in a flash memory device. The gate-coupling coefficient may have a substantial effect on an electric potential of a floating gate. In a flash memory device having a higher gate-coupling coefficient, the electric potential of the floating gate may be adjacent to a given electric potential of a control gate in the memory cell. Accordingly, performance of a flash memory cell may be improved, including programming and erasing efficiency and rapid reading speed.
The high gate-coupling rate may enable a simplification of chip design, and may lower an operation voltage of a flash memory cell to a lower power-source voltage. That is, an important element to determine the gate-coupling coefficient may be a capacitance between each polysilicon to a tunnel oxide capacitance, that is, a capacitance between a floating gate poly and a control gate poly. As the capacitance between each polysilicon increases and the tunnel oxide capacitance decreases, the gate coupling-coefficient may increase.
FIGS. 1A to 1C are cross section diagrams illustrating a related art method of manufacturing a flash memory device having a stack gate structure. The related art flash memory device may include semiconductor substrate 10, oxide film 11, floating gate poly film 12, ONO film 13, control gate poly film 14, Bottom AntiReflect Coating (BARC) 15, and photoresist pattern 16.
In the related art etching method, BARC 15 may be first etched using photoresist pattern 16 (as shown in FIG. 1B). Floating gate poly film 12, ONO film 13, and control gate poly film 14 may be subsequently etched (as shown in FIG. 1C).
In relation with the thickness of the stack gate of the related art flash memory device having a stack gate structure, control gate poly film 14, which may serve as a mask for ion implantation, may not be decreased in thickness if an ion-implantation condition is not changed on a decreased design rule. Thus, since a thickness of the film to be etched may not be decreased, it may be impossible to decrease the thickness of photoresist pattern 16 used as a mask in an etching process.
In this case, it may be necessary for the photoresist to maintain a thickness of 6000 Å at minimum. However, according to the decreased design rule, a pitch to form the stack gate, that is, a total value of line and critical dimension (CD) of space may also be decreased. Accordingly, it may be difficult to obtain a Depth of Focus (DOF) margin in an exposure process for the same thickness of the photoresist.
When patterning the photoresist of the stack gate, photoresist pattern 16 may be fallen or deformed. Also, even thought the photoresist pattern may be formed, its realization may be lowered and an efficiency of a flash memory device may deteriorate.